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STV7617D STV7617U
PLASMA DISPLAY PANEL SCAN DRIVER
. . . . . . . . .
PRELIMINARY DATA
64/65 SELECTABLE OUTPUT PLASMA DISPLAY DRIVER 100V ABSOLUTE MAXIMUM SUPPLY 5V SUPPLY FOR LOGIC 100/700mASOURCE/SINK OUTPUT 700mA SOURCE/SINK OUTPUT DIODE 65-BIT BIDIRECTIONAL SHIFT REGISTER (8MHz) HIGH IMPEDANCE OUTPUT CONTROL BCD TECHNOLOGY 100-PIN TQFP PACKAGE WITH INTEGRATED HEATSINK
TQFP100 (14 x 14 x 1.4mm Slug-down) (Thin Plastic Quad Flat Pack) ORDER CODE : STV7617D
DESCRIPTION The STV7617 is a scan driver for Plasma Display Panel (PDP) implemented in ST's proprietary BCD technology. Using a 65-bit cascadable 8MHz shift register, it drives 65 high current & high voltage outputs. The STV7617 can be configured either in 64 or 65 outputs depending on the SEL input Pin. By serialy connecting several STV7617, any vertical pixel definition canbe performed.The STV7617 is supplied with a separated 90V power output supply and a 5V logic supply. All command inputs are CMOS compatible. The STV7617 package is a 100-pin TQFP with integrated heatsink located on the bottom (STV7617D) or top (STV7617U) of the package.
November 1998
This is advance information on a new product now in development or undergoing evaluatio n. Details are subject to change without notice.
TQFP100 (14 x 14 x 1.4mm Slug-up) (Thin Plastic Quad Flat Pack) ORDER CODE : STV7617U
1/11
STV7617D - STV7617U
PIN CONNECTIONS (TQFP100 Slug-up)
OUT64 OUT65 SOUT VSSLOG VSSLOG OUT1 77 OUT2 76 75 74 73 72 71 70 69 68 67 66 65 CLK STB BLK SEL VSSP VSSP VSSP VSSP SIN F/R HIZ VCC VPP VPP VPP 79 NC NC VPP 78
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
OUT63 OUT62 OUT61 OUT60 OUT59 OUT58 OUT57 OUT56 OUT55 OUT54 OUT33 OUT52 OUT51 OUT50 OUT49 OUT48 OUT47 OUT46 OUT45 OUT44 OUT43 OUT42 OUT41 OUT40 OUT39
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
OUT3 OUT4 OUT5 OUT6 OUT7 OUT8 OUT9 OUT10 OUT11 OUT12 OUT13 OUT14 OUT15 OUT16 OUT17 OUT18 OUT19 OUT20 OUT21 OUT22 OUT23 OUT24 OUT25 OUT26 OUT27
STV7617U
TQFP100 (Top View)
64 63 62 61 60 59 58 57 56 55 54 53 52 51
2/11
7617U-01.EPS
OUT38
OUT37
OUT36
VSSSUB
OUT35
OUT34
OUT33
OUT32
OUT31
OUT30
OUT29
OUT28
NC
NC
NC
VPP
VSSP
VSSP
VSSP
VSSP
VSSP
NC
VPP
VPP
VPP
STV7617D - STV7617U
PIN CONNECTIONS (TQFP100 Slug-down)
OUT65 77 SOUT OUT2 OUT1 VSSLOG VSSLOG CLK STB BLK SEL VSSP VSSP VSSP VSSP SIN HIZ F/R VCC NC NC VPP VPP VPP OUT64 76 75 74 73 72 71 70 69 68 67 66 65 VPP 78
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
OUT3 OUT4 OUT5 OUT6 OUT7 OUT8 OUT9 OUT10 OUT11 OUT12 OUT13 OUT14 OUT15 OUT16 OUT17 OUT18 OUT19 OUT20 OUT21 OUT22 OUT23 OUT24 OUT25 OUT26 OUT27
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
79
OUT63 OUT62 OUT61 OUT60 OUT59 OUT58 OUT57 OUT56 OUT55 OUT54 OUT33 OUT52 OUT51 OUT50 OUT49 OUT48 OUT47 OUT46 OUT45 OUT44 OUT43 OUT42 OUT41 OUT40 OUT39
STV7617D
TQFP100 (Top View)
64 63 62 61 60 59 58 57 56 55 54 53 52 51
3/11
7617D-01.EPS
OUT36
OUT37
OUT28
OUT29
OUT30
OUT31
OUT32
OUT33
OUT34
OUT35
OUT38
NC
NC
NC
VSSSUB
VPP
VSSP
VSSP
VSSP
VSSP
VSSP
NC
VPP
VPP
VPP
STV7617D - STV7617U
PIN ASSIGNMENT (TQFP100)
Pin Number TQFP100 Slug-up 88 34-35-41-42 78-79-97-98 30-31-44-45 46-81-82-94-95 83-93 32 77 to 48, 40 to 36, 28 to 1, 100-99 91 90 89 87 86 85 84 92 29-33-43-47-80-96 TQFP100 Slug-down 88 34-35-41-42 78-79-97-98 30-31-32-45 46-81-82-94-95 83-93 44 99-100, 1 to 28, 36 to 40, 48 to 77 85 86 87 89 90 91 92 84 29-33-43-47-80-96 VCC VPP VSSP VSSLOG VSSSUB Supply Supply 5V Logic Supply High Voltage Supply of power outputs Symbol Type Function
Ground Ground of power outputs Ground Logic Ground Ground Substrate Ground Power Output Shift Register Data Output Clock of data shift register Latch of data to outputs Power Output Blanking Control Power Output High Impedance Control Shift Register Data Input Selection of number of power outputs Selection of shift direction Not connected
7617-01.TBL 7617-02.TBL
OUT1 to OUT 65 Output SOUT (SIN) CLK STB BLK HIZ SIN (SOUT) SEL F/R NC Output Input Input Input Input Input Input Input -
PIN ASSIGNMENT (Power Outputs)
Output Number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 Pin Number Slug-down Slug-up 77 99 76 100 75 1 74 2 73 3 72 4 71 5 70 6 69 7 68 8 67 9 66 10 65 11 64 12 63 13 62 14 61 15 60 18 59 17 58 18 57 19 56 20 Output Number 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 Pin Number Slug-do wn Slug-up 55 21 54 22 53 23 52 24 51 25 50 26 49 27 48 28 40 36 39 37 38 38 37 39 36 40 28 48 27 49 26 50 25 51 24 52 23 53 22 54 21 55 20 56 Output Number 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 Pin Number Slug-down Slug-up 19 57 18 58 17 59 16 60 15 61 14 62 13 63 12 64 11 65 10 66 9 67 8 68 7 69 6 70 5 71 4 72 3 73 2 74 1 75 100 76 99 77
4/11
STV7617D - STV7617U
BLOCK DIAGRAM
F/R SWITCH SEL CLK SIN (SOUT)
P1
65-BIT SHIFT REGISTER
P65
SOUT (SIN)
S1
S65
STB
Q1 Q2
LATCH
Q64Q65
V CC BLK VCC HIZ
VCC VSSSUB VSSP VSSLOG VPP
STV7617
VSSP
VPP
VSSP
VPP
7617-02.EPS
OUT1
OUT64 OUT65
CIRCUIT DESCRIPTION The STV7617 contains all the logic and the power circuits necessary to drive rows of a Plasma Display Panel (PDP). Data is shifted at each low to high transition of the (CLK) shift clock. After 64 or 65 shifts (depending on SEL) the first bit presented at (SIN) is available at the serial output (SOUT). This output can be used to cascade several drivers to perform any vertical resolution. CLK, STB, SIN and SOUT inputs are Smith trigger inputs. BLK and HIZ logical inputs are internally pulled to level "1". The maximum frequency of the shift clock is 8MHz. Shift register outputs (P1, ... P65) are transferred from the shift register into the latch stage when the latch input (STB) is at low level. Table 1 : Output State Configuration
STB * L H * * BLK L L L H H HIZ L H H L H Output State High impedance Inverted copy of input data Data latched Low level High level L H H H L H 64 65 65
Sustain current must not be sunk in the power outputs to VPP when the power supply is applied and output state is in HIZ or at high state. VSSSUB and VSSLOG must be connectedas closeas possible to the logical reference ground of the application. Table 2 : Shift Register Truth Table
F/R H H L L CLK Rise L or H Rise L or H SIN In In Out Out SOUT Out Out In In Comments Forward Shift Steady Reverse Shift Steady
Table 3 : Power Output Configuration
SEL L F/R L Number of Outputs 64 Comments Out1 is in Hi-Z mode (outputs 65 to 2 powered) Out65 is in Hi-Z mode (outputs 1 to 64 powered) Out 65 to Out 1 powered Out 1 to Out 65 powered
5/11
STV7617D - STV7617U
ABSOLUTE MAXIMUM RATINGS
Symbol VCC V PP VIN VOUT VPOUT IPOUT IDOUT Tjmax Toper Tstg Parameter Logic Supply (Pin 88) * Driver Supply (Pins 34, 35, 41, 42, 78, 79, 97, 98) * Logic Input Voltage (Pins 84, 86, 87, 89, 90, 91, 92) * Logic Output Voltage (Pin 85)* Driver Output Voltage (scanning mode) Driver Output Current (2)(4) Diode Output Current (3)(4) Junction Temperature Operating Temperature Storage Temperature Value -0.3, +7 -0.3, +100 -0.3, VCC + 0.3 -0.3, VCC + 0.3 -0.3, +100 -100, +700 700 +150 -20, +85 -50, +150 Unit V V V V V mA mA C C C
* In case of STV7617D
THERMAL DATA
7617-04.TBL 7617-05.TBL
Symbol Rth(j-a) Tjoper
Parameter Junction-ambient Typical Thermal Resistor (1) Maximum Operating Junction Temperature (1)
Value 25 125
Unit C/W C
Notes : 1. For TQFP100 packaging. 2. Through one power output. 3. Through all power outputs (see test diagram) : with Power dissipation lower or equal than Ptot and Junction temperature lower or equal than Tjmax and VPP = VSSP. 4. These parameters are measured during ST's internal qualification which includes temperature characterisation on standard batches and on corners batches of the process. These parameters are not tested on the parts.
ELECTRICAL CHARACTERISTICS (VCC = 5V, VPP = 90V, VSSP = 0V, VSSLOG = 0V, VSSSUB = 0V, T amb = 25C, fCLK = 8MHz, unless otherwise specified)
Symbol SUPPLY VCC ICCH ICCL VPP IPPH OUTPUT OUT1-OUT64 VPOUTH Power Output High Level VPOUTH Power Output High Level VPOUTL Power Output Low Level VDOUTH Output Diode High Level VDOUTL Output Diode Low Level SOUT VOH Logic Output High Level VOL Logic Output Low Level INPUT (CLK, STB, BLK, HIZ, SIN, SEL) VIH VIL IIH IIL Input High Level Input Low Level High Level Input Current Low Level Input Current CLK, SIN, STB, SEL BLK, HIZ 0.8 VCC 0.2 VCC 10 -10 -40 V V A A A IPOUTH = - 20mA IPOUTH = - 15mA, VPP = 40V IPOUTL = + 400mA IDOUTH = + 400mA (5)(6) IDOUTL = - 400mA (5)(6) IOH = - 1mA IOL = + 1mA 80 30 4 86 33 2.5 1.7 -1.2 4.2 0.1 5 5 -5 0.4 V V V V V V V Logic Supply Voltage Logic Supply Current Logic Supply Current Power Output Supply Voltage Power Output Supply Current (steady outputs) 4.5 20 5 5 5.5 100 90 100 V A mA V A Parameter Test Conditions Min. Typ. Max. Unit
fCLK = 8MHz
VIH = VCC VIL = 0V
Notes : 5. Compatible with power dissipation and Tjoper 125C. 6. See test diagram page 9.
6/11
7617-03.TBL
STV7617D - STV7617U
AC TIMINGS REQUIREMENTS (VCC = 4.5V to 5.5V, T amb = -20 to +85C, input signals max leading edge & trailing edge (tR, tF) = 10ns)
Symbol tWHCLK tWLCLK tSDAT tHDAT tDSTB tSSTB tSTB tBLK tHIZ Parameter Duration of clock (CLK) pulse at high level Duration of clock (CLK) pulse at low level Set-up Time of data input before clock (low to high) transition Hold Time of data input after clock (low to high) transition Minimum Delay to latch (STB) after clock (low to high) transition Set-up Time (STB) before clock (low to high) transition Latch (STB) Low Level Pulse Duration Blanking (BLK) Pulse Duration High Impedance (HIZ) Pulse Duration Min. 40 40 10 20 25 10 20 500 500 Typ. Max. Unit ns ns ns ns ns ns ns ns ns
7617-06.TBL 7617-07.TBL
AC TIMING CHARACTERISTICS (VCC = 5V,VPP = 90V,VSSP = 0V, VSSLOG = 0V, VSSSUB = 0V, Tamb = 25C, VILMax. = 0.2VCC, VIHMin. = 0.8VCC, VOH = 4.0V, V OL = 0.4V, unless otherwise specified)
Symbol tCLK tRDAT tFDAT tPHL1 tPLH1 tPHL2 tPLH2 tPHL3 tPLH3 tPHL4 tPLH4 tPHZ5 tPLZ5 tPZH5 tPZL5 tROUT tFOUT Data Clock Period Logical Data Output Rise Time Logical Data Output Fall Time Delay oflogic data output (high to low transition) afterclock (CLK)transition (C L = 10pF) Delay oflogic data output (low to high transition) afterclock (CLK)transition (C L = 10pF) Delay of power output change (high to low transition) after clock (CLK) transition Delay of power output change (low to high transition) after clock (CLK) transition Delay of power output change (high to low transition) after Latch (STB) transition Delay of power output change (low to high transition) after Latch (STB) transition Delay of power output change (high to low transition) to Blank (BLK) transition Delay of power output change (low to high transition) to Blank (BLK) transition Delay of power output change (high to Hi-Z transition) after high impedance (HIZ) (6) Delay of power output change (low to Hi-Z transition) after high impedance (HIZ) (6) Delay of power output change (Hi-Z to high transition) after high impedance (HIZ) (6) Delay of power output change (Hi-Z to low transition) after high impedance (HIZ) (6) Power Output Rise Time (7) Power Output Fall Time (7) Parameter Min. 125 Typ. Max. Unit 12 10 37 42 110 115 80 95 75 75 40 80 75 40 175 35 50 60 180 180 165 165 160 160 160 160 160 160 500 300 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Notes : 6. See test diagram page 9. 7. One output among 64, loading capacitor COUT = 200pF, other outputs at low level.
7/11
STV7617D - STV7617U
Figure 1 : AC Characteristics Waveform
tCLK tWHCLK tWLCLK "1" CLK 50% 50% tSDAT 50% "0" tHDAT "1" SIN 50% 50% "0" tFDAT SOUT 90% 10% tRDAT tPLH1 tSSTB tDSTB tSTB "1" STB tPHL2 90% 10% tPLH2 t BLK/POL "1" HIZ (BLK = H) 50% t PLH4 50% "0" tPHL4 90% OUTn 10% "0" tHIZ "1" HIZ (BLK = L) t ROUT 90% 10% 90% 10% t FOUT 50% tPHZ5 90% 10% tPLZ5 50% "0" tPZH5 60% 40% tPZL5 "1"
7617-03.EPS
tPHL1 "1" 90% 10% "0"
50%
50% "0" tPHL3 "1" 90% 10% "0" tPLH3
OUTn
"1"
OUTn
"0"
8/11
STV7617D - STV7617U
Figure 2 : Test Configuration
VPP VDOUTH OUTI VDOUTL VSSP VSSP IDOUTL IDOUTL OUTI VPP
Output sinking current as positive value, sourcing current as negative value
VPP OUT R VPP/2
HIZ Timing Measurement
INPUT/OUTPUT SCHEMATICS Figure 3 : BLK, HIZ Input
VCC
Figure 4 : F/R, SEL, CLK, STB Input
VCC
VCC
VCC
F/R, SEL CLK, STB
BLK, HIZ
GNDLOG
GNDLOG
7617-05.EPS
GNDSUB
GNDSUB
Figure 5 : SIN, SOUT Input
VCC VCC
Figure 6 : Power Output
VPP
SIN, SOUT VCC GNDLOG
7617-07.EPS 7617-08.EPS
OUT1 to OUT 65
GNDSUB
VSSP
9/11
7617-06.EPS
7617-04.EPS
VDOUT
STV7617D - STV7617U
PACKAGE MECHANICAL DATA : 100 PINS - THIN PLASTIC QUAD FLAT PACK (TQFP) (Slug-down)
S1 100 e A1 76 0,075 mm 0.03 inch 75
SEATING PLANE
A A2
1
25
51
E3 E1 E
S
26
D3 D1 D
50
L1
B
0,25 mm .010 inch
GAGE PLANE
K
Dimensions
Min.
Millimeters Typ.
10/11
1B.TBL
A A1 0.05 0.002 A2 1.35 1.40 0.053 B 0.17 0.22 0.007 C 0.09 0.004 D 16.00 D1 14.00 D3 12.00 e 0.50 E 16.00 E1 14.00 E3 12.00 L 0.45 0.60 0.75 0.018 L1 1.00 K 0o (Min.), 7o (Max.) Slug Dimension for L/Frame Pad Size 10.00 x 10.00mm H 9.85 S 8.80 0.346 S1 8.80 0.346
Max. 1.60 0.15 1.45 0.27 0.20
Min.
Inches Typ.
0.055 0.009 0.630 0.551 0.472 0.20 0.630 0.551 0.472 0.024 0.039
Max. 0.063 0.006 0.057 0.011 0.008
0.030
0.388
PM-1B.EPS
L
H
c
STV7617D - STV7617U
PACKAGE MECHANICAL DATA : 100 PINS - THIN PLASTIC QUAD FLAT PACK (TQFP) (Slug-up)
S1 100 e A1 76 75 0,075 mm 0.03 inch
SEATING PLANE
A A2
1
25
51
E3 E1 E
S
26
D3 D1 D
50
L1
B
H
c
0,25 mm .010 inch
GAGE PLANE
K
Dimensions
Min.
Millimeters Typ.
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No licence is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical comp onents in lifesupport devicesor systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics (c) 1998 STMicroelectronics - All Rights Reserved Purchase of I C Components of STMicroelectronics, conveys a license under the Philips I C Patent. 2 Rights to use these components in a I C system, is granted provided that the system conforms to 2 the I C Standard Specifications as defined by Philips. STMicroelectronics GROUP OF COMPANIES Australia - Brazil - Canada - China - France - Germany - Italy - Japan - Korea - Malaysia - Malta - Mexico - Morocco - The Netherlands Singapore - Spain - Sweden - Switzerland - Taiwan - Thailand - United Kingdom - U.S.A. http://www.st.com
2 2
11/11
4S.TBL
A A1 0.05 0.002 A2 1.35 1.40 0.053 B 0.17 0.22 0.007 C 0.09 0.004 D 16.00 D1 14.00 D3 12.00 e 0.50 E 16.00 E1 14.00 E3 12.00 L 0.45 0.60 0.75 0.018 L1 1.00 K 0o (Min.), 7o (Max.) Slug Dimension for L/Frame Pad Size 10.00 x 10.00mm H 9.85 S 8.80 0.346 S1 8.80 0.346
Max. 1.60 0.15 1.45 0.27 0.20
Min.
Inches Typ.
0.055 0.009 0.630 0.551 0.472 0.20 0.630 0.551 0.472 0.024 0.039
Max. 0.063 0.006 0.057 0.011 0.008
0.030
0.388
PM-4S.EPS
L

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